Why Big Quantum Computers May Stay Impossible

In the paper's words

Universal gate‑based quantum computers promise exponential speed‑ups for problems such as integer factorisation, yet commercial‑scale devices remain absent. The gap originates from physical limits that are not captured by the abstract class BQP. We formalise a new class BQP_physical that incorporates three concrete constraints: (i) finite signal‑propagation latency across macroscopic processor dimensions, (ii) a correlated‑error floor that grows with qubit count, and (iii) a coherence‑time budget consumed by quantum error correction.

The abstract, verbatim; every line below is quoted from the text.

What it claims

that any Shor‑scale processor with N≈10⁴ qubits exceeds the fault‑tolerance threshold under realistic correlated‑error and latency parameters—would be falsified by an experimental demonstration of a fault‑tolerant logical operation on a processor with N>10 qubits, a measured correlated‑error coefficient α < 10^-6, and a total logical error per operation below 10^-3 while respecting the latency bound. Conversely, observation of a correlated‑error floor α ≥ 10^-5 for such a processor would reinforce the claim.

Numbers it reports

1. Using a processor dimension of 10 m, a per‑gate error target of $10^{-3}$, a correlated‑error coefficient of $10^{-5}$ per qubit pair, and a typical superconducting gate duration of 20 ns, we derive (a) a total propagation latency of $33~\mu\text{s}$ for a depth‑$10^{3}$ circuit, (b) a maximal viable qubit count of approximately 10 when the logical error budget is relaxed to $10^{-2}$, and (c) a logical error probability exceeding 1 for a Shor‑scale processor with $N=10^{4}$ qubits.

   from Abstract

2. Gate duration : The 20 ns gate time reflects superconducting qubits; other platforms (e.g., trapped ions) have longer gates, worsening the QEC budget.

   from 6.1 Limitations

3. Observation of $p_{\text{corr}} \lt 10^{-6}$ with 95 % confidence would falsify the current bound; observation of $p_{\text{corr}} \ge 10^{-5}$ would reinforce it.

   from 7. Practical Implications and Engineering Pathways

4. (e) Projected cost and performance bounds (projection) Assuming a modular architecture with ten modules each containing 1000 qubits, the cryogenic infrastructure cost scales as $$ C \approx 10 \times 5~\text{M\$} = 50~\text{M\$}, $$ where $5~\text{M\$}$ per module is derived from current dilution‑refrigerator pricing (projection).

   from 7. Practical Implications and Engineering Pathways

5. Even if we cap the probability at 1, the effective error per logical operation is 100 %, rendering error correction impossible.

   from 4.6 Large‑Scale Shor Scenario ($N = 10^{4}$)

6. (c) Minimal next experiment A de‑risking experiment consists of fabricating a modest 100‑qubit processor with 1 mm inter‑qubit spacing, performing simultaneous randomized benchmarking on all qubits, and extracting the correlated‑error probability $p_{\text{corr}}$.

   from 7. Practical Implications and Engineering Pathways

How it is done

1. Using a processor dimension of 10 m, a per‑gate error target of $10^{-3}$, a correlated‑error coefficient of $10^{-5}$ per qubit pair, and a typical superconducting gate duration of 20 ns, we derive (a) a total propagation latency of $33~\mu\text{s}$ for a depth‑$10^{3}$ circuit, (b) a maximal viable qubit count of approximately 10 when the logical error budget is relaxed to $10^{-2}$, and (c) a logical error probability exceeding 1 for a Shor‑scale processor with $N=10^{4}$ qubits.

   from Abstract

2. Physical realizability of quantum dynamical models has been studied in the context of linear quantum optics. [1] proves that for a class of passive optical components the strict bounded‑real property guarantees physical realizability and provides a low‑frequency error bound for approximations.

   from 2. Background and Related Work

3. We formalise BQP_physical as the set of decision problems solvable by a uniform family of quantum circuits $\{C_n\}$ that satisfy three explicit resource bounds.

   from 3. Methods

4. Each physical gate has an independent error probability $p$.

   from 3.2 Correlated‑Error Floor Model

What would falsify it

1. The central claim—that any Shor‑scale processor with $N\approx10^{4}$ qubits exceeds the fault‑tolerance threshold under realistic correlated‑error and latency parameters—would be falsified by an experimental demonstration of a fault‑tolerant logical operation on a processor with $N\gt 10$ qubits, a measured correlated‑error coefficient $\alpha \lt 10^{-6}$, and a total logical error per operation below $10^{-3}$ while respecting the latency bound.

   from 6.2 Falsifiability

2. Discussion of falsifiability, limitations, and engineering pathways (Sections 6–7).

   from 1. Introduction

3. Observation of $p_{\text{corr}} \lt 10^{-6}$ with 95 % confidence would falsify the current bound; observation of $p_{\text{corr}} \ge 10^{-5}$ would reinforce it.

   from 7. Practical Implications and Engineering Pathways

Where the claim stops

1. Assumption of uniform correlated coefficient $\alpha$ : Real devices may exhibit spatially varying noise; the model treats $\alpha$ as constant.

   from 6.1 Limitations

2. Processor geometry : The linear dimension $L = 10~\text{m}$ is a simplifying assumption; three‑dimensional integration could reduce $\tau_{\text{prop}}$.

   from 6.1 Limitations

3. Error‑budget linearisation : The total logical error is approximated as a simple sum of independent, correlated, and latency terms, neglecting higher‑order interactions.

   from 6.1 Limitations

Where to read

1. Abstract186 words · 1 min
2. 1. Introduction349 words · 2 min
3. 2. Background and Related Work278 words · 1 min
4. 3. Methods327 words · 1 min
5. 4. Analysis651 words · 3 min
6. 5. Results107 words · 1 min
7. 6. Discussion225 words · 1 min
8. 7. Practical Implications and Engineering Pathways356 words · 2 min
9. 8. Conclusion92 words · 1 min
10. Provenance and AI Involvement225 words · 1 min