Ultrametric p-Adic Arithmetic as Energy-Proportional Precision Computing: An Energy Model for Digit-Terminable Multiply-Accumulate

In the paper's words

Fixed-width Archimedean floating-point arithmetic pays a constant energy cost per multiply-accumulate (MAC) regardless of the precision actually required by the computation. We conjecture and formalize an alternative: p-adic (ultrametric) number representations, whose digits are hierarchically ordered by the p-adic valuation, permit computation to terminate after k digits once the required precision is met. We derive an energy model for digit-serial p-adic MAC in which energy scales as O(k²) in the number of retained digits, and compare it against reported CMOS floating-point MAC energies of $3.7$ pJ at 45 nm and $0.9$ pJ at 7 nm.

The abstract, verbatim, and its opening sentence is the claim. Every line below is quoted from the text.

Numbers it reports

1. Energy per precision bit: $k e_d + e_a = 0.071$ pJ/bit at $k = 7$, versus $0.15416666666666667$ pJ/bit for binary32 at 45 nm — a $46.0\%$ lower per-bit cost (ratio $0.071/0.15416666666666667 = 0.4606$).

   from 5. Results

2. The comparison against $3.7$ pJ and $0.9$ pJ floating-point MAC energies inherits whatever methodology produced those figures; node-to-node comparison at fixed $e_d$ is inconsistent, since $e_d$ should also shrink at 7 nm, which would lower $k^*(7)$ below our computed 9 if $e_d$ scaled by the same factor as $E_f$ (e.g., $e_d \to 0.01 \times 0.9/3.7 = 0.00243$ pJ gives $k^*(7) = \lfloor \sqrt{0.9/0.00243} \rfloor = \lfloor \sqrt{370.4} \rfloor = 19$, restoring parity in break-even precision while lowering absolute energies).

   from 6. Discussion

3. A third falsifier: demonstrating that precision-scheduling overhead (control, conversion, irregular memory access) exceeds the computed per-MAC savings of $3.203$ pJ at 45 nm.

   from 6. Discussion

4. We derive an energy model for digit-serial p-adic MAC in which energy scales as $O(k^2)$ in the number of retained digits, and compare it against reported CMOS floating-point MAC energies of $3.7$ pJ at 45 nm and $0.9$ pJ at 7 nm.

   from Abstract

5. Under a stated bit-cell energy assumption of $e_d = 0.01$ pJ per digit-product at 45 nm, we compute a break-even precision of $k^* = 19$ binary p-adic digits at 45 nm and $k^* = 9$ at 7 nm.

   from Abstract

6. For a quantization tolerance of $\varepsilon = 10^{-2}$, requiring $k = 7$ digits, the p-adic MAC costs $0.497$ pJ versus $3.7$ pJ, an $86.57\%$ saving at 45 nm and $44.78\%$ at 7 nm.

   from Abstract

How it is done

1. We derive an energy model for digit-serial p-adic MAC in which energy scales as $O(k^2)$ in the number of retained digits, and compare it against reported CMOS floating-point MAC energies of $3.7$ pJ at 45 nm and $0.9$ pJ at 7 nm.

   from Abstract

2. This work formulates a p-adic analogue of Borel's theorem, relating regulators of higher $K$-groups of number fields to special values of zeta-functions via syntomic regulators and p-adic $L$-functions, and conjectures the precise relation between the p-adic and classical situations.

   from 2. Background and Related Work

3. We define the model inputs, each stated explicitly: $e_d$: energy of one digit-digit product-and-accumulate (a $\lceil \log_2 p \rceil \times \lceil \log_2 p \rceil$-bit multiply plus small add) in a digit-serial p-adic array.

   from 3.2 Energy model

4. With $e_a \ll e_d$ we use the leading term for the break-even digit count: $$k^* = \left\lfloor \sqrt{\frac{E_f}{e_d}} \right\rfloor.$$

   from 3.4 Break-even condition

What would falsify it

1. We analyze conditions under which ultrametric architectures beat Archimedean ones in joules per compute, discuss off-chip communication as a labeled projection, and state the assumptions, failure modes, and falsifiers of the model.

   from Abstract

2. A silicon or RTL-level demonstration showing that a digit-serial p-adic MAC's measured energy per operation does not fall below the fixed-width floating-point MAC for any $k \le k^*$ would falsify the core conjecture under our assumptions.

   from 6. Discussion

3. A third falsifier: demonstrating that precision-scheduling overhead (control, conversion, irregular memory access) exceeds the computed per-MAC savings of $3.203$ pJ at 45 nm.

   from 6. Discussion

Where the claim stops

1. The coefficient $e_d = 0.01$ pJ is an assumption, not a measurement or a synthesis-tool extraction.

   from 6. Discussion

2. (ii) The p-adic absolute value is not the Archimedean one: error tolerances stated in real-relative terms ($|e|/|x| \le \varepsilon$ over $\mathbb{R}$) do not translate directly to $|\cdot|_p$ bounds without an embedding or scaling convention; our $p^{-k} \le \varepsilon$ step assumes the quantity of interest has $|x|_p \le 1$, which fails for quantities with negative p-adic valuation, where more digits are needed.

   from 6. Discussion

3. A silicon or RTL-level demonstration showing that a digit-serial p-adic MAC's measured energy per operation does not fall below the fixed-width floating-point MAC for any $k \le k^*$ would falsify the core conjecture under our assumptions.

   from 6. Discussion

Where to read

1. Abstract212 words · 1 min
2. 1. Introduction423 words · 2 min
3. 2. Background and Related Work776 words · 3 min
4. 3. Methods420 words · 2 min
5. 4. Analysis910 words · 4 min
6. 5. Results274 words · 1 min
7. 6. Discussion577 words · 3 min
8. 7. Conclusion184 words · 1 min