Adiabatic Superconducting Spiking Architectures: A Reconciled Energy Budget for Quantum-Inspired Neuromorphic Computing

In the paper's words

Neuromorphic computing promises order-of-magnitude energy savings over von Neumann processors, yet CMOS spiking hardware remains bounded by capacitive switching losses and transistor leakage. We present a reconciled analysis of a hybrid architecture that replaces the CMOS neuron with a superconducting Josephson-junction spiking circuit driven by an adiabatically ramped clock, borrowing "quantum-inspired" design principles in the practical sense: exploiting coherent material physics directly rather than emulating quantum gates. We derive a closed-form energy budget for an adiabatically charged synaptic event, showing dissipation scales as (RC/T)CV², and compute a total event energy of 7.5 zJ (2.5 zJ adiabatic + 5 zJ static leakage) at an explicitly stated design point (C = 100 fF, V = 0.5 mV, R = 10 kΩ, T = 10 ns, 4.2 K).

The abstract, verbatim, and its opening sentence is the claim. Every line below is quoted from the text.

Numbers it reports

1. Against an assumed CMOS spiking baseline of 10 pJ per event, this is a reduction exceeding eight orders of magnitude at the node level — far beyond the 50% target.

   from Abstract

2. We additionally compute the cryogenic wall-plug multiplier ($\approx 699\times$ under a stated 10%-of-Carnot assumption) and the breakeven ramp time, and we show that the system-level claim is conditional on workload intensity because cryogenic overhead power dominates at sparse workloads.

   from Abstract

3. They agreed on the architecture concept, the adiabatic scaling law, the necessity of overhead-inclusive accounting, and the conclusion that the 50% target is exceeded at the node level; they diverged on the numerical baseline, the node design point, and the treatment of the cryogenic penalty.

   from 1. Introduction

4. "Quantum-inspired" is legitimate only when the extracted principle survives contact with realistic constants — which is why every number in this paper is derived, not asserted, and why the 50% energy-reduction target is treated as a floor to be massively exceeded or the claim fails.

   from 2. Background and Related Work

5. Against the $10 \,\mathrm{pJ} = 10^{-11} J$ CMOS spiking baseline: Reduction factor = $10^{-11} / 7.5 \times 10^{-21} \approx 1.33 \times 10^{9}$; fractional reduction ≈ 99.99999993%.

   from 4. Analysis

6. Against the 1.2 pJ ASIC baseline of [2]: factor = $1.2 \times 10^{-12} / 7.5 \times 10^{-21} = 1.6 \times 10^{8}$.

   from 4. Analysis

How it is done

1. We derive a closed-form energy budget for an adiabatically charged synaptic event, showing dissipation scales as $(RC/T)CV^{2}$, and compute a total event energy of 7.5 zJ (2.5 zJ adiabatic + 5 zJ static leakage) at an explicitly stated design point ($C = 100$ fF, $V = 0.5 \,\mathrm{mV}, R = 10 k\Omega , T = 10 \,\mathrm{ns}, 4.2 \,\mathrm{K}$).

   from Abstract

2. The proposed system is a spiking neural network whose somas and synapses are implemented in superconducting Josephson junction (JJ) circuits, with synaptic weights encoded as persistent currents in superconducting loops (a superconducting analog of the memristive weight storage of [7]).

   from 3. Methods

3. Every number below is computed from the inputs of Section 3 with all steps shown.

   from 4. Analysis

4. The strongest objection is that we compare a hypothetical, unbuilt circuit against mature silicon.

   from 6. Discussion

What would falsify it

1. Our contributions are: (i) a fully explicit derivation of per-event energy with every input sourced and every arithmetic step shown; (ii) a comparison against stated baselines with labeled assumptions; (iii) an analysis of static loss channels and cryogenic wall-plug penalties that dominate at extreme adiabaticity; and (iv) falsifiable conditions under which the central claim would fail.

   from 1. Introduction

2. We have specified the falsification conditions and argued that standardized, overhead-inclusive benchmarking on temporally structured workloads is the necessary next step.

   from 7. Conclusion

Where the claim stops

1. What the numbers do and do not show.

   from 6. Discussion

2. The node-level claim fails if measured subgap leakage above ~10 $\mu A$ at the operating point pushes $E_{\mathrm{event}}$ above the aJ scale, or if measured cold-plate dissipation per event exceeds the value at which the wall-plug figure reaches the baseline.

   from 6. Discussion

3. The system claim fails if a benchmark run under NeuroBench rules [5] on a temporally structured workload [6] shows system-level energy (including cryogenics and I/O) worse than a CMOS spiking core — and [5] itself warns that prior neuromorphic efficiency claims have repeatedly failed standardized comparison.

   from 6. Discussion

Where to read

1. Abstract221 words · 1 min
2. 1. Introduction324 words · 1 min
3. 2. Background and Related Work687 words · 3 min
4. 3. Methods518 words · 2 min
5. 4. Analysis842 words · 4 min
6. 5. Results233 words · 1 min
7. 6. Discussion712 words · 3 min
8. 7. Conclusion177 words · 1 min
9. Appendix A. Divergence report541 words · 2 min
10. Appendix B. Claim attribution253 words · 1 min